First Principles Fieldbook
Circuit Foundations

Voltage Divider Loading: A Worked Paper Example

First Principles Fieldbook · Updated 2026-09-08 · 7 min read
Voltage Divider Loading: A Worked Paper Example
AbstractVoltage divider loading is the change in a divider's output when the connected load draws current. In an ideal resistive DC model, a load across the lower resistor changes that branch's equivalent resistance and therefore the division ratio. Treat the following calculations as paper analysis, not construction or testing instructions. Physical equipment requires manufacturer documentation, approved procedures and people qualified for its hazards; a calculated voltage does not establish safety.
Contents

What is voltage divider loading?

Voltage divider loading is the change in a divider's output when the connected load draws current. In an ideal resistive DC model, a load across the lower resistor changes that branch's equivalent resistance and therefore the division ratio. Treat the following calculations as paper analysis, not construction or testing instructions. Physical equipment requires manufacturer documentation, approved procedures and people qualified for its hazards; a calculated voltage does not establish safety.

This lesson uses an original fictional circuit to separate two questions: what the unloaded equation predicts, and what changes when the model includes a load. No equipment was built, powered or measured. The arithmetic was checked computationally; that is not a bench test or a claim that a particular product behaves this way.

If the symbols are unfamiliar, begin with Ohm's law explained. Here we use that relationship to analyse a network rather than one isolated resistor.

Which connections does the paper model assume?

The ideal input source holds node A at +3.3 V relative to reference node B. An upper resistor R1 connects A to the output node X. A lower resistor R2 connects X to B. The output, Vout, means the potential of X relative to B.

The load resistor RL, when included, also connects X to B. This connection table defines the model; it is not a physical wiring plan:

Model element First node Second node Assumed value
Ideal voltage source A, positive B, reference 3.3 V
R1, upper resistor A X 10 kΩ
R2, lower resistor X B 10 kΩ
RL, load resistor X B 10 kΩ when present
Output definition X B Vout

Reference node B is the mathematical zero-voltage reference for this analysis, not an instruction to connect anything to protective earth.

The source is ideal and fixed. All three resistors, when present, are ideal, positive and constant. We exclude component tolerances, temperature changes, source resistance and time-varying behaviour. These exclusions define the question being solved; they do not assert that such effects are absent from real equipment.

A two-resistor divider's unloaded output follows Vout = Vin × R2/(R1 + R2). Analog Devices explains this ratio in its voltage-divider glossary. The lower resistor belongs in the numerator because our output is defined across that resistor.

What happens before the load is included?

Without RL, the hypothetical resistors total 20 kΩ, or 20,000 Ω. The predicted output is:

Vout = 3.3 V × 10 kΩ / (10 kΩ + 10 kΩ) = 1.65 V.

The resistor units cancel within the ratio. Both values must use consistent units: entering 10 for one resistor and 10,000 for the other would describe unequal resistances if your calculator treats both entries as ohms.

An independent arithmetic check uses current. The source current is 3.3 V / 20,000 Ω = 0.000165 A, or 165 microamperes. Multiplying that current by the lower resistance gives 0.000165 A × 10,000 Ω = 1.65 V.

The two routes agree. That agreement supports this calculation under its stated assumptions. It does not tell us what happens after the topology changes. “The resistors are equal, so the output is half” is incomplete unless the output-loading assumption travels with it.

Why is the load parallel with R2?

R2 and RL share both nodes, X and B. They are parallel branches, not three resistors in one series chain. The Analog Devices and Digilent course text defines parallel elements by their shared pair of nodes and gives the equivalent resistance for two parallel resistors as their product divided by their sum. Real Analog, Chapter 2, sections 2.1–2.2.

Call the lower branch's equivalent resistance Rp:

Rp = (R2 × RL) / (R2 + RL).

For our fictional equal 10 kΩ values:

Rp = (10 kΩ × 10 kΩ) / (10 kΩ + 10 kΩ) = 5 kΩ.

Now use Rp in place of the unloaded lower resistance:

Vout = 3.3 V × 5 kΩ / (10 kΩ + 5 kΩ) = 1.1 V.

Neither original 10 kΩ resistor changed its assumed value. Adding the parallel branch changed the equivalent lower resistance. This distinction matters when describing loading: the network changed, not the nominal value printed beside R2.

Do not substitute 30 kΩ for the total. That would correspond to a different connection pattern. Read the node pairs before choosing which resistances to add or combine in parallel.

Where does the current go in the loaded example?

The ideal source now sees 15 kΩ, giving 3.3 V / 15,000 Ω = 0.000220 A, or 220 microamperes. That is the current through R1.

Both lower branches have 1.1 V across 10,000 Ω, so each carries 0.000110 A, or 110 microamperes. The branch currents sum to 220 microamperes, matching the upper-resistor current.

The output fell even though the input stayed fixed:

Name that percentage's denominator. Relative to the 3.3 V input, the same difference is approximately 16.67%. Both calculations are arithmetically valid, but they answer different questions. A worksheet headed simply “error percent” leaves the reader guessing which comparison was intended.

These values describe our invented model. They are not measured accuracy figures, recommended component values or an acceptable-error specification.

How does changing the load resistance change the prediction?

Keep the source and both divider resistors fixed. Changing only RL produces this original calculation table:

Assumed RL Equivalent lower resistance Rp Predicted Vout Reduction from 1.65 V
No load branch 10 kΩ 1.65000 V 0%
10 kΩ 5 kΩ 1.10000 V 33.33%
100 kΩ approximately 9.09091 kΩ approximately 1.57143 V 4.76%
1 MΩ approximately 9.90099 kΩ approximately 1.64179 V 0.50%

Displayed decimal places are for comparing the calculations, not a claim of measurement precision. Each percentage uses the unrounded calculated output and the same 1.65 V unloaded reference.

For this fixed, positive-resistance model, a larger RL draws less load current and brings the output closer to the unloaded prediction. The table does not establish a universal “large enough” resistance. That decision would need a defined allowable deviation and an appropriate model of the actual receiving circuit.

As a paper exercise, suppose an invented requirement permits no more than 1% reduction from 1.65 V under these assumptions. The 100 kΩ row does not meet that narrow requirement; the 1 MΩ row does. This is an analysis comparison, not approval to use either value in a product.

Why isn't a real device automatically a fixed resistor?

An electronic input may need a more detailed model. Analog Devices' application note on ADC source resistance describes effects involving input impedance, sampling capacitance and acquisition time. An analog-to-digital converter, or ADC, cannot automatically be represented by our constant RL for every operating condition. The note expressly warns against applying its illustrative performance numbers to another design. ADC source-resistance analysis.

We therefore assign no real device to RL. We also do not recommend the divider as a regulated power supply. Analog Devices' glossary explains that divider output resistance affects the voltage delivered to a load; a nominal unloaded ratio is not a promise of constant output under use.

For a real design review, the exact device documentation and intended operating conditions would be needed. A qualified designer must decide whether the simplified model is appropriate. Do not fill missing input behaviour with a guessed resistance simply because it makes the equation solvable.

What belongs in a finished calculation record?

Our suggested paper-analysis record contains the node table, source assumption, resistor values, load model, equations, unrounded results, displayed rounding and comparison reference. Add one sentence stating what was excluded.

A suitable conclusion is: “The ideal DC model predicts 1.1 V with the specified 10 kΩ load, compared with 1.65 V with no load branch.” An unsuitable conclusion is: “The equipment has been tested and is safe.” Nothing in this exercise supplies that evidence.

Our verification and validation guide explains how an analysis result can support a particular requirement without establishing every intended-use claim.

Keep this lesson on paper. Do not open, probe, energize or modify equipment to reproduce it. Energized systems, mains or building wiring, batteries, stored energy, unknown equipment and hazardous testing require appropriately qualified people and applicable manufacturer, laboratory or workplace procedures. More conceptual lessons are collected in circuit foundations.

Sources

FAQ

Why did the equal-resistor divider stop producing half the input?

In the fictional model, the load adds a second branch between the output and reference nodes. Its parallel combination with the lower resistor is 5 kΩ, while the upper resistor remains 10 kΩ. The resulting ratio predicts 1.1 V from 3.3 V. Neither original resistor changed its assigned value.

Can I add all three resistor values together?

Not for the connections defined here. The lower resistor and load share both endpoint nodes, so first calculate their parallel equivalent. Add that equivalent to the upper resistance only after this reduction. A sum of all three values would analyse a different topology, not the loaded divider in the node table.

Does 1 MΩ always count as a negligible load?

No universal conclusion follows from that number alone. In this particular ideal example it produces approximately 0.50% reduction relative to the unloaded output. Whether that meets a requirement depends on the allowed deviation and whether the assumed model fits. The example is not a component-selection rule for real equipment.

Does the calculation tell me how to build or test a divider?

No. It is a paper exercise with an ideal source and resistors, not an equipment procedure. Do not energize, probe or modify hardware based on it. Follow manufacturer documentation and approved laboratory or workplace procedures; energized systems, mains, stored energy and hazardous testing belong with appropriately qualified people.

How should I report the output reduction?

State both the absolute difference and the denominator used for any percentage. Here the difference is 0.55 V; dividing by the unloaded 1.65 V gives approximately 33.33%. Keep the unrounded calculation for checking, label displayed rounding, and do not imply that the decimal places represent measured precision.